■ Separate Independent read and write data ports
   ❐ Supports concurrent transactions
■ 300 MHz to 375 MHz clock for high bandwidth
■ 4-Word Burst for reducing address bus frequency
■ Double Data Rate (DDR) interfaces on both read and write ports (data transferred at 750 MHz) at 375 MHz
■ Read latency of 2.0 clock cycles
■ Two input clocks (K and K) for precise DDR timing
   ❐ SRAM uses rising edges only
■ Echo clocks (CQ and CQ) simplify data capture in high speed systems
■ Single multiplexed address input bus latches address inputs for both read and write ports
■ Separate Port Selects for depth expansion
■ Data valid pin (QVLD) to indicate valid data on the output
■ Synchronous internally self-timed writes
■ Available in x8, x9, x18, and x36 configurations
■ Full data coherency providing most current data
■ Core VDD = 1.8V ± 0.1V; IO VDDQ = 1.4V to VDD[1]
■ Available in 165-Ball FBGA package (13 x 15 x 1.4 mm)
■ Offered in both Pb-free and non Pb-free packages
■ Variable drive HSTL output buffers
■ JTAG 1149.1 compatible test access port
■ Delay Lock Loop (DLL) for accurate data placement